wv3hg2128m72eeu-d6 august 2006 rev. 1 advanced* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 2gb ? 2x128mx72 ddr2 sdram unbuffered dimm description the wv3hg2128m72eeu is a 2x128mx72 double data rate ddr2 sdram high density module. this memory module consists of eighteen 128mx8 bit with 4 banks ddr2 synchronous drams in fbga packages, mounted on a 240-pin dimm fr4 substrate. * this product is under development, is not quali ed or characterized and is subject to change or cancellation without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option ? parity function features ? unbuffered 240-pin, dual in-line memory module ? fast data transfer rates: pc2-6400*, pc2-5300*, pc2-4300 and pc2-3200 ? v cc = v ccq = 1.8v ? v ccspd = +1.7v to +3.6v ? differential data strobe (dqs, dqs#) option ? four-bit prefetch architecture ? dll to align dq and dqs transitions with ck ? multiple internal device banks for concurrent operation ? supports duplicate output strobe (rdqs/rdqs#) ? programmable cas# latency (cl): 3, 4, 5* and 6* ? adjustable data-output drive strength ? on-die termination (odt) ? serial presence detect (spd) with eeprom ? auto & self refresh (64ms/8,192 cycle refresh) ? gold edge contacts ? dual rank ? rohs compliant ? package option ? 240 pin dimm ? 30.00mm (1.181") typ operating frequencies pc2-6400* pc2-5300* pc2-4300 pc2-3200 clock speed 400mhz 333mhz 266mhz 200mhz cl-t rcd -t rp 6-6-6 5-5-5 4-4-4 3-3-3 * consult factory for availability
wv3hg2128m72eeu-d6 advanced 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 pin configuration pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1v ref 61 a4 121 v ss 181 v cc 2v ss 62 v cc 122 dq4 182 a3 3 dq0 63 a2 123 dq5 183 a1 4 dq1 64 v cc 124 v ss 184 v cc 5v ss 65 v ss 125 dm0 185 ck0 6 dqs0# 66 v ss 126 nc 186 ck0# 7 dqs0 67 v cc 127 v ss 187 v cc 8v ss 68 nc 128 dq6 188 a0 9 dq2 69 v cc 129 dq7 189 v cc 10 dq3 70 a10/ap 130 v ss 190 ba1 11 v ss 71 ba0 131 dq12 191 v cc 12 dq8 72 v cc 132 dq13 192 ras# 13 dq9 73 we# 133 v ss 193 cs0# 14 v ss 74 cas# 134 dm1 194 v cc 15 dqs1# 75 v cc 135 nc 195 odt0 16 dqs1 76 cs1# 136 v ss 196 a13 17 v ss 77 odt1 137 ck1 197 v cc 18 nc 78 v cc 138 ck1# 198 v ss 19 nc 79 v ss 139 v ss 199 dq36 20 v ss 80 dq32 140 dq14 200 dq37 21 dq10 81 dq33 141 dq15 201 v ss 22 dq11 82 v ss 142 v ss 202 dm4 23 v ss 83 dqs4# 143 dq20 203 nc 24 dq16 84 dqs4 144 dq21 204 v ss 25 dq17 85 v ss 145 v ss 205 dq38 26 v ss 86 dq34 146 dm2 206 dq39 27 dqs2# 87 dq35 147 nc 207 v ss 28 dqs2 88 v ss 148 v ss 208 dq44 29 v ss 89 dq40 149 dq22 209 dq45 30 dq18 90 dq41 150 dq23 210 v ss 31 dq19 91 v ss 151 v ss 211 dm5 32 v ss 92 dqs5# 152 dq28 212 nc 33 dq24 93 dqs5 153 dq29 213 v ss 34 dq25 94 v ss 154 v ss 214 dq46 35 v ss 95 dq42 155 dm3 215 dq47 36 dqs3# 96 dq43 156 nc 216 v ss 37 dqs3 97 v ss 157 v ss 217 dq52 38 v ss 98 dq48 158 dq30 218 dq53 39 dq26 99 dq49 159 dq31 219 v ss 40 dq27 100 v ss 160 v ss 220 ck2 41 v ss 101 sa2 161 cb4 221 ck2# 42 cb0 102 nc 162 cb5 222 v ss 43 cb1 103 v ss 163 v ss 223 dm6 44 v ss 104 dqs6# 164 dm8 224 nc 45 dqs8# 105 dqs6 165 nc 225 v ss 46 dqs8 106 v ss 166 v ss 226 dq54 47 v ss 107 dq50 167 cb6 227 dq55 48 cb2 108 dq51 168 cb7 228 v ss 49 cb3 109 v ss 169 v ss 229 dq60 50 v ss 110 dq56 170 v cc 230 dq61 51 v cc 111 dq57 171 cke1 231 v ss 52 cke0 112 v ss 172 v cc 232 dm7 53 v cc 113 dqs7# 173 nc 233 nc 54 ba2 114 dqs7 174 nc 234 v ss 55 nc 115 v ss 175 v cc 235 dq62 56 v cc 116 dq58 176 a12 236 dq63 57 a11 117 dq59 177 a9 237 v ss 58 a7 118 v ss 178 v cc 238 v cc spd 59 v cc 119 sda 179 a8 239 sa0 60 a5 120 scl 180 a6 240 sa1 pin names pin name function a0-a13 address inputs ba0,ba2 sdram bank address dq0-dq63 data input/output cb0-cb7 check bits dqs0-dqs8 data strobes dqs0#-dqs8# data strobes complement dm0-dm8 data masks odt0, odt1 on-die termination controls ck0,ck0#-ck2,ck2# clock inputs cke0, cke1 clock enables cs0#, cs1# chip selects ras# row address strobe cas# column address strobe we# write enable sa0-sa2 spd address sda spd data input/output scl spd clock input v cc power supply v ss ground v ref power supply reference v cc spd spd power nc spare pins, no connect
wv3hg2128m72eeu-d6 advanced 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 functional block diagram cs0# dqs0 dqs0# dm0 dm/ rdqs cs# dqs dqs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs1 dqs1# dm1 dqs2 dqs2# dm2 dqs3 dqs3# dm3 dqs5 dqs5# dm5 dqs4 dqs4# dm4 dqs6 dqs6# dm6 dqs7 dqs7# dm7 cs1# cs1# ba0-ba2 a0-a13 ras# cas# we# cke0 cke1 odt0 odt1 ba0-ba2: ddr 2 sdrams a0-a13: ddr 2 sdrams ras#: ddr 2 sdrams cas#: ddr 2 sdrams we#: ddr 2 sdrams cke0: ddr 2 sdrams cke1: ddr 2 sdrams odt0: ddr 2 sdrams odt1: ddr 2 sdrams cs0# cs1#: ddr 2 sdrams cs0#: ddr 2 sdrams a0 serial pd a1 a2 sa0 sa1 sda scl *wire per clock loading table/wiring diagrams notes: 1. dq, dm, dqs/dqs# resistors: 5.1 ohms +/-5% 2. bax, ax ras#, cas#, we# resistors: 5.1 ohms +/- 5% *clock wiring clock input ddr2 sdrams *ck0/ck0# *ck1/ck1# *ck2/ck2# 6 ddr2 sdrams 6 ddr2 sdrams 6 ddr2 sdrams sa2 wp dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v ccspd serical pd ddr2 sdrams ddr2 sdrams ddr2 sdrams v cc\ v ccq vref v ss dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dqs8 dqs8# dm8 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# note: all resistor values are 22 ohms unless otherwise speci ed.
wv3hg2128m72eeu-d6 advanced 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 dc operating conditions all voltages referenced to v ss parameter symbol min typical max unit notes supply voltage v cc 1.7 1.8 1.9 v 3 i/o reference voltage v ref 0.49 x v cc 0.50 x v cc 0.51 x v cc v1 i/o termination voltage v tt v ref -0.04 v ref v ref +0.04 v 2 spd supply voltage v ccspd 1.7 - 3.6 v notes: 1 v ref is expected to equal v cc/2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed +/-1 percent of the dc value. peak-to-peak ac noise on v ref may not exceed +/-2 percent of v ref . this measurement is to be taken at the nearest v ref bypass capacitor. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 3. v ccq of all ic's are tied to v cc . absolute maximum ratings symbol parameter min max units v cc voltage on v cc pin relative to v ss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 c i l input leakage current; any input 0v wv3hg2128m72eeu-d6 advanced 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 operating temperature condition parameter symbol rating units notes operating temperature (commercial) toper 0oc to 85oc oc 1, 2 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, p lease refer to jedec jesd51.2. 2. at 0 - 85 oc, operation temperature range, all dram speci cation will be supported. input dc logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih(dc) v ref + 0.125 v cc + 0.300 v input low (logic 0) voltage v il(dc) -0.300 v ref - 0.125 v input ac logic level all voltages referenced to v ss parameter symbol min max units ac input low (logic 1) voltage ddr2-400 & ddr2-533 v il(ac) v ref + 0.250 v ac input high (logic 1) voltage ddr2-667 v ih(ac) v ref + 0.200 v ac input low (logic 0) voltage ddr2-400 & ddr2-533 v il(ac) v ref - 0.250 v ac input low (logic 0) voltage ddr2-667 v il(ac) v ref - 0.200 v
wv3hg2128m72eeu-d6 advanced 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 ddr2 i cc specifications and conditions ddr2 sdram components only symbol proposed conditions 806 665 553 403 units i cc0* operating one bank active-precharge current; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 918 873 828 ma i cc1* operating one bank active-read-precharge current; i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ), t rcd = t rcd (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc 4w tbd 1,008 963 918 ma i cc2p* precharge power-down current; all banks idle; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd 216 216 216 ma i cc2q** precharge quiet standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating tbd 720 630 630 ma i cc2n** precharge standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching tbd 810 720 720 ma i cc3p** active power-down current; all banks open; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 tbd 540 450 450 ma slow pdn exit mrs(12) = 1 tbd 216 216 216 ma i cc3n** active standby current; all banks open; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 900 810 810 ma i cc4w* operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1,503 1,278 1,143 ma i cc4r* operating burst read current; all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc 4w tbd 1,503 1,278 1,143 ma i cc5b** burst auto refresh current; t ck = t ck (i cc ); refresh command at every t rfc (i cc ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 3,960 3,870 3,780 ma i cc6** self refresh current; ck and ck\ at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal tbd 180 180 180 ma i cc7* operating bank interleave read current; all bank interleaving reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = t rc d(i cc )-1*t ck (i cc ); t ck = t ck (i cc ), t rc = t rc (i cc ), t rrd = t rrd (i cc ), t rcd = 1*t ck (i cc ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching. tbd 2,808 2,628 2,448 ma note: i cc speci cation is based on samsung components. other dram manufacturers speci cation may be different. *: value calculated as one module rank in this operating condition, and all other module ranks in i cc2p (cke low) mode. **: value calculated re ects all module ranks in this operating condition.
wv3hg2128m72eeu-d6 advanced 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 ac timing parameters & specifications ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit clock clock cycle time cl = 6 t ck (6) tbd tbd ps cl = 5 t ck (5) tbd tbd 3,000 8,000 ps cl = 4 t ck (4) tbd tbd 3,750 8,000 3,750 8,000 5,000 8,000 ps cl = 3 t ck (3) tbd tbd 5,000 8,000 5,000 8,000 5,000 8,000 ps ck high-level width t ch tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck ck low-level width t cl tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck half clock period t hp tbd tbd min (t ch, t cl ) min (t ch, t cl ) min (t ch, t cl )ps clock jitter t jit tbd tbd -125 125 -125 125 -125 125 ps data dq output access time from ck/ck# t ac tbd tbd -450 +450 -500 +500 -600 +600 ps data-out high-impedance window from ck/ck# t hz tbd tbd t ac(max) t ac(max) t ac(max) ps data-out low-impedance window from ck/ck# t lz tbd tbd t ac(min) t ac(max) t ac(min) t ac(max) t ac(min) t ac(max) ps dq and dm input setup time relative to dqs t ds tbd tbd 100 100 150 dq and dm input hold time relative to dqs t dh tbd tbd 225 225 275 dq and dm input pulse width (for each input) t dipw tbd tbd 0.35 0.35 0.35 t ck data hold skew factor t qhs tbd tbd 340 400 450 ps dq?dqs hold, dqs to rst dq to go nonvalid, per access t qh tbd tbd t hp - t qhs t hp - t qhs t hp - t qhs ps data valid output window (dvw) t dvw tbd tbd t qh - t dqsq t qh - t dqsq t qh - t dqsq ns data strobe dqs input high pulse width t dqsh tbd tbd 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl tbd tbd 0.35 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck tbd tbd -400 +400 -450 +450 -500 +500 ps dqs falling edge to ck rising ? setup time t dss tbd tbd 0.2 0.2 0.2 t ck dqs falling edge from ck rising ? hold time t dsh tbd tbd 0.2 0.2 0.2 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq tbd tbd 240 300 350 ps dqs read preamble t rpre tbd tbd 0.9 1.1 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs write preamble setup time t wpres tbd tbd 000ps dqs write preamble t wpre tbd tbd 0.35 0.35 0.35 t ck dqs write postamble t wpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck write command to rst dqs latching transition t dqss tbd tbd wl- 0.25 wl+ 0.25 wl- 0.25 wl+ 0.25 wl- 0.25 wl+ 0.25 t ck address and control input pulse width for each input t ipw tbd tbd 0.6 0.6 0.6 t ck address and control input setup time t is tbd tbd 200 250 250 ps address and control input hold time t ih tbd tbd 275 375 475 ps address and control input hold time t ccd tbd tbd 222 t ck * ac speci cation is based on samsung components. other dram manufactures speci cation may be different. continued on next page
wv3hg2128m72eeu-d6 advanced 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 ac timing parameters (cont'd) ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit command and address active to active (same bank) command t rc tbd tbd 55 55 55 ns active bank a to active bank b command t rrd tbd tbd 7.5 7.5 7.5 ns active to read or write delay t rcd tbd tbd 15 15 15 ns four bank activate period t faw tbd tbd 37.5 37.5 37.5 37.5 37.5 37.5 ns active to precharge command t ras tbd tbd 40 70,000 40 70,000 40 70,000 ns internal read to precharge command delay t rtp tbd tbd 7.5 7.5 7.5 ns write recovery time t wr tbd tbd 15 15 15 ns auto precharge write recovery + precharge time t dal tbd tbd t wr +t rp t wr +t rp t wr +t rp ns internal write to read command delay t wtr tbd tbd 7.5 7.5 7.5 ns precharge command period t rp tbd tbd 15 15 15 ns precharge all command period t rpa tbd tbd t rp +t ck t rp +t ck t rp +t ck ns load mode command cycle time t mrd tbd tbd 222t ck cke low to ck,ck# uncertainty t delay tbd tbd t is +t ck t ih t is +t ck t ih t is +t ck t ih ns self refresh refresh to active of refresh to refresh command interfal t rfc tbd tbd 127.5 70,000 127.5 70,000 127.5 70,000 ns average periodic refresh interval t refi tbd tbd 7.8 7.8 7.8 s exit self refresh to non-read command t xsnr tbd tbd t rfc(min) +10 t rfc(min) +10 t rfc(min) +10 ns exit self refresh to read command t xsrd tbd tbd 200 200 200 t ck exit self refresh timing reference t isxr tbd tbd t is t is t is ps odt odt turn-on delay t aond tbd tbd 222222t ck odt turn-on t aon tbd tbd t ac(min) t ac(max) +1000 t ac(min) t ac(max) +1000 t ac(min) t ac(max) +1000 ps odt turn-off delay t aofd tbd tbd 2.5 2.5 2.5 2.5 2.5 2.5 t ck odt turn-off t aof tbd tbd t ac(min) t ac(max) +600 t ac(min) t ac(max) +600 t ac(min) t ac(max) +600 ps odt turn-on (power-down mode) t aonpd tbd tbd t ac(min) +2000 2 x t ck + t ac(max) +1000 t ac(min) +2000 2 x t ck + t ac(max) +1000 t ac(min) +2000 2 x t ck + t ac(max) +1000 ps odt turn-off (power-down mode) t aofpd tbd tbd t ac(min) +2000 2.5 x t ck + t ac(max) +1000 t ac(min) +2000 2.5 x t ck + t ac(max) +1000 t ac(min) +2000 2.5 x t ck + t ac(max) +1000 ps odt to power-down entry latency t anpd tbd tbd 333t ck odt power-down exit latency t axpd tbd tbd 888t ck power-down exit active power-down to read command, mr[bit12=0] t xard tbd tbd 222t ck exit active power-down to read command, mr[bit12=1] t xards tbd tbd 7-al 6-al 6-al t ck a exit precharge power-down to any non- read command. t xp tbd tbd 222t ck cke minimum high/low time t cke tbd tbd 333t ck * ac speci cation is based on samsung components. other dram manufactures speci cation may be different.
wv3hg2128m72eeu-d6 advanced 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 30.50 (1.201) 29.85 (1.175) pin 1 17.80 (0.700) typ. 5.0 (0.197) typ. 123.0 (4.843) typ. 1.0 (0.039) typ. 0.80 (0.032) typ. 4.00 (0.158) (4x) pin 120 front view 133.50 (5.256) 133.20 (5.244) 63.0 (2.480) typ. 55.0 (2.165) typ. 10.00 (0.394) typ. back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 4.00 (0.158) max 1.50 (0.059) 3.00 (0.118) (4x) 5.175 (0.204) (2x) package dimensions for d6 ** all dimensions are in millimeters and (inches) ordering information for d6 part number speed/data rate frequency cas latency t rcd t rp height** wv3hg2128m72eeu806d6xxg* 400mhz/800mb/s 6 6 6 30.00mm (1.181") typ wv3hg2128m72eeu665d6xxg* 333mhz/667mb/s 5 5 5 30.00mm (1.181") typ wv3hg2128m72eeu534d6xxg 266mhz/533mb/s 4 4 4 30.00mm (1.181") typ wv3hg2128m72eeu403d6xxg 200mhz/400mb/s 3 3 3 30.00mm (1.181") typ * contact factory for availability notes: ? rohs compliant product. (g = rohs compliant) ? vendor speci c part numbers are used to provide memory component source control. the place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. consult factory for quali ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
wv3hg2128m72eeu-d6 advanced 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 part numbering guide wv 3 h g 2 128m 72 e e u xxx d6 x x g wedc memory (sdram) ddr 2 gold dual rank depth bus width component width (x8) 1.8v unbuffered speed (mb/s) package 240 pin industrial temp option (for commercial leave "blank" for industrial add "i") component vendor name (m = micron) (s = samsung) g = rohs compliant
wv3hg2128m72eeu-d6 advanced 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs august 2006 rev. 1 document title 2gb ? 2x128mx72 ddr2 sdram unbuffered dram die options: ? samsung: b-die ? micron: u28a: a-die, move to u38z: d-die q4'06 and u48b: e-die q2'07 revision history rev # history release date status rev 0 created june 2006 concept rev 1 1.0 moved to advanced august 2006 advanced
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